Field of the Invention
The invention relates in general to an adaptive memory address translation method and a memory controller using the same, and more particularly to an adaptive memory address translation method applied to a high bandwidth and low voltage system and a memory controller using the same.
Description of the Related Art
When data are read from or written into a memory, the data cannot be accessed until the steps of activating, instruction reading/writing and pre-charging are successively performed. When the access address of the memory is switched, whether the page address and the bank address are hit or not affects the performance of the overall system.
FIG. 1 (Prior Art) is a schematic illustration showing an example of accessing a memory. FIG. 2 (Prior Art) is a timing chart showing access instructions of FIG. 1. In FIG. 1, if the data at the bank address C and the page address D are to be firstly accessed, and then the data at the bank address E and the page address F are to be accessed, then the condition that the page address is not hit and the bank address is not hit may occur. Because the next page address to be accessed is at a different bank address, after the activating step is performed at the bank address C, as shown in FIG. 2, the memory can first activate the bank address E in a pipeline manner to decrease the loss of the system performance.
However, if the condition that the page address is not hit but the bank address is hit occurs, the loss of the system performance may occur. FIG. 3 (Prior Art) is a schematic illustration showing another example of accessing the memory. FIG. 4 (Prior Art) is a timing chart showing access instructions of FIG. 3. In FIG. 3, if the data at the bank address A and the page address A are to be accessed firstly and then the data at the bank address A and the page address B are to be accessed, then the condition that the page address is not hit but the bank address is hit may occur. Because the memory has to pre-charge the page address A in the bank address A and then re-activate the next page address B to be accessed, the activating step shown in FIG. 4 cannot be hidden in the pipeline manner, and the system performance is decreased.
Consequently, the arrangement of the memory addresses relates to whether the overall system can effectively access the memory, so that the performance of the overall system is affected.
In addition, the memory receives the memory address in a single-end signaling manner. So, when the continuous memory addresses, received by the memory, need to carry, most bits simultaneously change to cause the instantaneously significant change of the current, and thus affect the electric property, such that the translation speed between the logic 1 and logic 0 is decreased. This causes the memory to sample the incorrect memory address and disables the memory from normally working in the higher working speed.